— Open Source Hardware User Group

Event #9 — Chips (Programmable Logic, Computer Conservation with FPGAs, OpenCores & OpenRISC 1000)

On the 21st April 2011, 18:00 - 20:00 at Skills Matter, 116-120 Goswell Road, London, EC1V 7DP, UK [map] (51.525335, -0.099056)

Please register to attend.

Programmable logic, and in particular field-programmable gate arrays (FPGAs), is a topic that has frequently come up at OSHUG meetings, both in informal discussion and in presentations (see use of FPGAs in projects covered at OSHUG #5 & OSHUG #8).

This is a particularly exciting technology in the context of open source hardware, as it presents an opportunity to realise performance gains approaching those that are associated with custom silicon – an Application-Specific Integrated Circuit (ASIC) - albeit without the enormous foundry start-up costs which make this largely the reserve of major industry. Furthermore, the design artefacts lend themselves to collaborative development and can be handled in a manner similar to that employed with the source code to computer software.

At the ninth OSHUG meeting we will be given an introduction to programmable logic and the associated development cycle, we'll hear about applications in computer conservation, and we will learn about open source chip design, the OpenCores community and the MIPS-like OpenRISC 1000 CPU.

A Brief Introduction to Programmable Logic

Programmable Logic Devices - mainly FPGAs – are frequently utilised in high speed and computationally intensive applications, and with modern devices containing several million transistors and many gigabits/second of connectivity they are becoming increasingly popular in the race to achieve exascale computing power.

But what does this all mean and how can FPGAs achieve this processing power? How do they differ from the good old CPUs we have in our everyday computers?

In essence, an FPGA is a device that contains configurable blocks of logic along with flexible interconnect between these blocks. They can be configured to contain exactly and only those operations that appear in the algorithms employed in a particular application, which can potentially give them quite a bit of an advantage in terms of throughput and efficiency when compared to static instruction set processors such as a traditional x86 CPU.

In this short introductory talk we will cover the basics of programmable logic devices and talk about the design, synthesis, simulation, implementation and programming cycles associated with FPGA projects.

Omer Kilic is a research student at the University of Kent working on dynamically reconfigurable architectures and embedded systems. When he is not busy working on his PhD project (a reconfigurable heterogeneous computing framework) or running lab classes, he enjoys tinkering and drinking good beer.

Computer Conservation with FPGAs

Having acquired an IBM System/360 Model 30 mainframe whilst he was at university, Lawrence Wilkinson brought it back to life, then abandoned it when the rent and power costs became a drain, and has since felt very guilty. As they became obsolete in the early 1970s, very few IBM System/360s now exist in running order. To make amends he embarked on a project of re-creating the Model 30 as a gate-level simulation, using the original circuits and microcode. While the software-based Hercules emulator is available to run all 360 and 370 software, Lawrence's programmable logic-based solution faithfully replicates the Model 30 with its limited storage and I/O capability, and provides a front panel interface. The basic CPU is implemented in a Xilinx S3 FPGA and the VHDL is available for download under the GPL. Development of the project continues with the further addition of storage and I/O devices.

Lawrence Wilkinson started out as an Electrical and Electronic Engineer in Auckland in the 1980s, transmogrified into an IT and Accounting support person in the late 80s, then went back to hardware and low-level software upon moving to England in the mid 90s. Eventually ending up with the new BAR Formula 1 team, he spent a few years writing and supporting on-car control software, won the World Championship with Brawn Grand Prix in 2009, and currently supports various factory test systems for Mercedes-Benz Grand Prix in Northamptonshire.

OpenCores, Chip Design and the OpenRISC 1000

Opencores dates back to 1999 as a forum for open source chip designs, primarily intended for FPGA, but also used in ASIC. It now hosts several hundred designs, and has over 100,000 registered users world wide.

This talk will look at what is involved in putting together an open source chip design. In particular the licensing issues represent a challenge, with standard F/OSS licenses having serious weaknesses when it comes to licensing hardware.

It will finish with an overview of OpenCores' flagship project, the OpenRISC 1000. This is a 32-bit MIPS-like RISC processor, with a full reference SoC design. It comes with a GNU development tool chain, a number of RTOS ports and an up to date uClibc Linux kernel/BusyBox implementation. In recent years the entire front-end design flow has become open source, as open source electronic design automation (EDA) tools have become available. It has now reached the stage of maturity where some of its development is by commercially funded engineers, as well as a large community of volunteers.

Dr Jeremy Bennett is Chief Executive of Embecosm Limited. Embecosmi provides open source services, tools and models to facilitate embedded software development with complex systems-on chip. He spends two days a month working as the Embedded Systems Champion for the Electronics, Sensors and Photonics KTN, which seeks to improve the flow of knowledge between academia and industry. He can be contacted via jeremy.bennett@embecosm.com.

Note: Please aim to arrive for 18:00 - 18:20 as the event will start at 18:30 prompt.

To add your photographs to ones shown here, upload them to Flickr with the tag "oshug:event=9". You might also like to join the OSHUG Flickr Pool.